Micro Architect - Quantum Solution - Santa Clara, CA

The company has grown to a 250-person semiconductor startup with operations in the U.S., India and Russia.

Soft Machines is in the business of licensing and co-developing Soft Machines VISC™ architecture-based microprocessor and SoC products for IoT, mobile and cloud markets.

Corporate headquarters are in Santa Clara, California, USA, with international operations in India and Russia.

Soft Machines investors include Samsung Ventures, AMD, Mubadala, RVC, KACST, RUSNANO, TAQNIA and other strategic investors.

As the CPU Micro Architect you will own: Microarchitecture definition, development and specification.

Starting with NEW high-level architectural model, through micro-architectural research and arriving at a detailed specification.
As RTL Engineer you will own development, assessment and refinement of RTL design to target power, performance, area and timing goals.
Validation - Support testbench development and simulation for functional and performance verification. Performance exploration and correlation
Explore high performance strategies and validate that the RTL design meets targeted performance.
Work with design team members across disciplines (Logic, Circuits, PD, DFT) to implement and validate physical design on the aspects of timing, area, reliability, testability and power.

This role calls for 10+ years of CPU Microarchitecture and RTL design experience.

Thorough knowledge of microprocessor architecture (ARM|x86|SPARC|MIPS) including expertise in one (1) or more of the following areas:

SOC/GPU/CPU/NPU: Coherency, Cache (Data, Instruction Cache, L2, L3)

CPU: Out-of-order processor design (Scheduler, Load Store Unit/Load Store Queue, Instruction fetch, Branch predictor)

Execution Unit Design : Floating Point Unit (FPU) or Integer arithmetic (ALU)

Memory Management Unit (MMU)) & Memory subsystems

Knowledge of logic design principles along with timing and power implications.

Expert in low power microarchitecture techniques.

Expert in high performance techniques and trade-offs in a CPU microarchitecture.

View the Job here